1. Field of the Invention
The present invention relates to a memory testing apparatus suitable for testing a memory such as, for example, a flash memory.
2. Description of the Related Art
Heretofore, a direct current (DC) test has been performed for a memory in addition to a functional test therefor. The DC test means a test which checks, in the state that a predetermined voltage is being applied to a terminal of a memory under test (the memory is generally constructed in the form of a semiconductor integrated circuit (IC)), whether or not a predetermined current can be taken out from that terminal, or checks, in the state that a predetermined current is being taken out from a terminal of a memory under test, whether or not a voltage of that terminal can be maintained at a predetermined voltage, or the like. The former is called current measuring test under voltage applied to a memory under test and the latter is called voltage measuring test under current applied to a memory under test.
FIG. 5 is a block diagram showing a general construction of an example of the circuit configuration necessary for performing a DC test provided in a conventional semiconductor integrated circuit testing apparatus (IC testing apparatus), specifically, an IC memory testing apparatus. The illustrated IC memory testing apparatus (hereinafter referred to simply as a memory testing apparatus) includes a controller 1, a pattern generator 2, and a direct current (DC) test unit 3. The controller 1 is generally constructed by a computer system and controls the operations of a plurality of units in the memory testing apparatus through a control bus line BUS. In the illustrated example, units controlled by the controller 1 are only the pattern generator 2 and the DC test unit 3. However, it is needless to say that the other units not shown are also controlled by this controller 1.
The pattern generator 2 generates a test signal TS having a predetermined pattern to be applied to a memory under test, an address signal, a control signal and the like. In a DC test, the pattern generator 2 supplies a test signal TS having a predetermined pattern to a memory cell of a specified address of a memory under test (MUT) 4 and the DC test unit 3 measures a voltage or a current of a specified terminal of this memory under test 4, as shown by a line 10 with arrows at its opposite ends, to perform a DC test. This DC test is performed for each of the terminals of the memory under test 4.
The DC test is performed as follows.
(1) The DC test is started by supplying a pattern generation command PGS to the pattern generator 2 from the controller 1 via the control bus line BUS.
(2) The pattern generator 2 supplies an initialization pattern signal, upon receiving the pattern generation command PGS, to the memory under test 4 to initialize the state of the memory under test 4.
(3) After the initialization, the pattern generator 2 applies a test signal TS having a predetermined pattern to a memory cell of an address of the memory under test 4 specified by an address signal and enters a hold mode in which the pattern is inhibited from being updated. Then the pattern generator 2 sends to the controller 1 a pattern hold signal PGH indicating that the pattern generator 2 has entered the hold mode.
(4) The controller 1 supplies, upon receiving the pattern hold signal PGH, a DC test start command DCS to the DC test unit 3 to activate the DC test unit 3 thereby causing the unit to start the DC test.
(5) The DC test unit 3 measures a voltage or a current of a specified terminal of the memory under test 4 and sends the measurement result MEC to the controller 1.
(6) The controller 1 compares the measurement result (a voltage value or a current value) sent from the DC test unit 3 with a reference value to determine whether the memory cell is defective (failure) or not. If the measurement result departs or differs from the reference value, the memory cell at that address is determined to be a failure one and its address is stored in a memory. When the address of the failure memory cell is stored in the memory, the DC test of that address is completed.
(7) The controller 1 supplies a control command PGCON for proceeding to a next step to the pattern generator 2 to reset the hold mode of the pattern generator 2 and to update the address of the memory under test 4 to which a test signal is to be supplied and the pattern of the test signal. Then the controller 1 applies a test signal having the updated pattern to a memory cell at the updated address. Then the pattern generator 2 enters a hold mode again in which the pattern is inhibited from being updated.
(8) Thereafter, the above operations (4)-(7) are repeated for memory cells of all the addresses of the memory under test 4.
(9) When the DC test for one specified terminal is completed, the same DC test is performed for next one specified terminal.
In such a way, the DC tests are sequentially performed for all the terminals of the memory under test 4.
Incidentally, in case of a flash memory which is a flash electrically erasable programmable read only memory or another non-volatile memories (memories the stored contents of which are not erased even if the power supply is turned off), there is a case a next process to be performed may be selected depending on the result of the DC test.
As an example of this case, methods such as described below are employed. That is, when a measured voltage of a specified terminal is out of the reference range in, for example, H side (higher potential side), writing operations of a test pattern signal are repeated for a memory cell of an address to which the test pattern signal was applied. After the writing operations are repeated predetermined times or more, the test is performed again. Further, when a measured voltage is out of the reference range in L side (lower potential side), erasing operations of the test pattern signal already written in the memory cell of the address are repeated. When the number of erasing operation times reaches a predetermined value, a process that the test is performed again or the like is performed.
Therefore, the conventional memory testing apparatus is arranged such that a decision or determination function is provided in the controller 1 wherein a failure state as to whether the voltage or current measured by the DC test unit 3 is out of the reference range in H side or L side is determined by the controller 1 based on the measured value from the DC test unit 3, and then a control signal for the operation to be performed in next step is supplied to the pattern generator 2 in accordance with the failure state.
As mentioned above, in the conventional memory testing apparatus, the controller 1 intervenes in all the steps except step (2), i.e., steps (1), (3), (4), (5), (6), (7), (8) and (9). Since, particularly in the case where the memory under test 4 is a flash memory, the DC test is performed for each terminal of the memory under test 4 at all the addresses of thereof, the number of control operations of the controller 1 becomes huge and the time period required for the control becomes, if accumulated, also very long. In addition, in the case of a flash memory, since the conventional memory testing apparatus is arranged such that a condition for operating the pattern generator 2 in the next step is selected, as mentioned above, based on the decision operation of the controller 1 depending upon the state at the time a failure has occurred, the number of operation times of the controller 1 is increased more and more. As a result, there is a drawback in the conventional memory testing apparatus that the time period required for a DC test becomes considerably long. That is, there is a disadvantage that a DC test cannot be completed in a short time period.